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Preliminary W583XXX HIGH FIDELITY Power Speech TM
GENERAL DESCRIPTION
W583xxx are fabricated using the Winbond CMOS process. The W583xxx family is a new member of the PowerSpeech synthesizer series, with voice quality which is even better than before. The W583xxx family has adopted the same architecture as the PowerSpeech synthesizers while replacing the 4-bit ADPCM algorithm with Winbonds new high fidelity voice synthesis algorithm to produce better quality voice. W583xxx provides IR function, CPU interface, pad option for Ring or Crystal oscillator and voice output in DAC current or PWM type. According different voice duration, there are 11 bodies in W583xxx family, list them below. PART NO. Duration PART NO. Duration W583S10 10 sec W583S50 50 sec W583S15 15 sec W583S60 60 sec W583S20 20 sec W583S80 80 sec W583S25 25 sec W583S99 99 sec W583S30 30 sec W583M02 120 sec W583S40 40 sec
Notes: 1. The voice duration is estimated by 6.4 KHz sampling rate. 2. W583S10 provides less I/O pins, and do not provide crystal oscillator.
FEATURES
* Programmable speech synthesizer * New high fidelity synthesis algorithm * Wide operating voltage range: 2.4 - 5.5 Volts * Direct drive speaker by PWM output or Built-in 8-bit D/A converter * Supports CPU interface operation * IR interface for command Transmission and Receiving * Symbolic compiler supported * Instruction cycle 400 S typically * Section control
- Variable frequency: 4.8/6/8/12 KHz - LED: ON/OFF
* Eight general-purpose registers R0-R7 * Pad option for Ring or Crystal oscillator * 8 STOP outputs
3 1 2
* 8 trigger inputs - with separate control of falling/rising edge trigger * Number of interrupt vector / label up to 2,048
Notes: 1. W583S10 provide ring oscillator only. 2. Only 4 trigger pins in W583S10. 3. Only 5 STOP outputs in W583S10.
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Publication Release Date: March 1999 Revision A1
Preliminary W583XXX
BLOCK DIAGRAM
W583S15 to W583M02
RESET OSC/XIN XOUT SEL TG1 : TG3/IRIN : TG8 STPA/BUSY STPB LED2/STPC : STPH LED1
TIMING GENERATOR ROM
CONTROLLER
SPEECH SYNTHESIZER
D/A CONVERTER PWM DRIVER
VDD1 VSS1
IROUT VDD VSS TEST
AUD/SPK+ SPK-
W583S10
RESET OSC OSCO TG1 TG2 TG3/IRIN TG4 STPA/BUSY STPB LED2/STPC STPD STPE LED1 IROUT VDD VSS TEST AUD/SPK+ SPKD/A CONVERTER PWM DRIVER VDD1 VSS1
TIMING GENERATOR
ROM
CONTROLLER
SPEECH SYNTHESIZER
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Preliminary W583XXX
PIN DESCRIPTION
NAME VDD TEST
RESET
I/O I I I I I Positive power supply
DESCRIPTION Test pin, internally pulled low Reset all, functions as POR, internally pulled high Direct trigger input 1, internally pulled high Direct trigger input 2, internally pulled high Direct trigger input 3 or IR input, internally pulled high. Once this pin is pulled low, the oscillation circuit is active even the chip enters standby mode. Direct trigger input 4, internally pulled high Negative power supply LED1 output IR signal output pin, active low Stop signal A or Busy signal Stop signal B LED2 output or Stop signal C Stop signal D Stop signal E Current type output or PWM output for speaker PWM output Negative power supply Positive power supply
TG1 TG2 TG3/IRIN
TG4 VSS LED1 IROUT STPA/BUSY STPB LED2/STPC STPD STPE AUD/SPK+ SPKVSS1 VDD1
I O O O O O O O O O -
Pin Description only for W583S15 to W583M02
NAME OSC/XIN XOUT SEL TG5 TG6 TG7 I/O I I/O I I I I DESCRIPTION Ring oscillator input or crystal input Crystal input or oscillator clock output Ring/Crystal oscillator select, internally pulled high. Floating for Ring and grounded for crystal. Direct trigger input 5, internally pulled high Direct trigger input 6, internally pulled high Direct trigger input 7, internally pulled high
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Publication Release Date: March 1999 Revision A1
Preliminary W583XXX
Pin Description only for W583S15 to W583M02, continued
NAME TG8 STPF STPG STPH
I/O I O O O Stop signal F Stop signal G Stop signal H
DESCRIPTION Direct trigger input 8, internally pulled high
Pin Description only for W583S10
NAME OSC OSCO I/O I O Ring oscillator input Oscillator clock output DESCRIPTION
FUNCTIONAL DESCRIPTION
The W583xxx is a derivative of Winbond's PowerSpeech synthesizers, which are becoming dominant in the consumer market, especially for toy applications. There are up to 8 trigger inputs and 8 STOP outputs in W583xxx. The maximal number of software key pad by scanning matrix is up to 8 x 9 = 72 keys. There are 8 general purpose registers, R0-R7. R0-R7 can apply not only for "LD" and "JP" instructions but also for "MV" instruction. Only R0 can apply for "INC" instruction. CPU interface is the same as the W581xx series. IR interface is a new feature of PowerSpeech. User can use IR interface to transmit and receive a command. For example, when X chip executes the "TX R1" instruction, the Pulse Position Modulation waveform (with 38 KHz carrier) outputs from IROUT pin to drive a photo diode. Y chips within a certain distance will receive the IR signal through an IR receiver module to TG3/IRIN pin and execute a "JP" instruction to the interrupt vector/label pointed by R1 of X chip. There are two kinds of events that can cause the W583xxx to enter the POI (Power On Initialization) process: one is power on, and the other is direct trigger from RESET pin. The interrupt vector "32" is allocated for this special event, and its priority is above all, i.e., no triggers can override the POI process if they all happen simultaneously. So the user can write a program into this interrupt vector to set the power on initial state. If the user does not wish to execute a program on power on, he should write an "END" instruction in interrupt vector "32". During the POI process, triggers can then override it successfully; if the EN0, EN1 and MODE0, MODE1 registers are set properly. If more than two events happen simultaneously, the priority that is set by the internal H/W is: POI > TG1F > TG1R > TG2F > TG2R > TG3F > TG3R > TG4F > TG4R > TG5F > TG5R > TG6F > TG6R > TG7F > TG7R > TG8F > TG8R > "JP" instruction.
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Preliminary W583XXX
Register Definition And Control
The register file of the W583xxx family is composed of 14 registers, including 8 general purpose registers and 6 special purpose registers. They are defined to facilitate the operations for various purposes. The default setting values of the registers are given in the following table. REGISTER General Register Special Register R0-R7 EN0, EN1 MODE0, MODE1 STOP PAGE NAME DEFAULT SETTING 00100000B 11111111B 11111111B 11111111B 00000000B
Note: EN1 register and bits 5-7 of STOP register are not provided in W583S10.
1. MODE0 Register BIT 7 6 5 4 3, 1, 0 2 DESCRIPTION LED mode LED2/STPC pin selection IR output source Debounce time Reserved STPA/BUSY pin selection 1: Flash 0: DC 1: LED2 output 0: STPC output 1: Hardware control IR output 0: STPC control IR output 1: Long 0: Short 1: STPA output 0: BUSY output DEFINITION
MODE0.7 controls the output type of LED1 (and LED2) pin. MODE0.6 controls the configuration of LED2/STPC pin. MODE0.5 controls the output source of IR. If hardware control IR output is selected, IR output can have signal with carrier or without carrier which is selected by MODE1.0. MODE0.4 controls the trigger pin debounce time. MODE0.2 controls the behavior of the STPA/BUSY pin which is usually used as Busy signal in CPU mode.
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Publication Release Date: March 1999 Revision A1
Preliminary W583XXX
2. MODE1 Register BIT 7, 6, 1 5 4 3 2 0 DESCRIPTION Reserved LED Flash Type LED1 Section Control LED2 Control LED1 Volume Control IR Output Format 1: Alternate 0: Synchronous 1: YES 0: NO 1: SECTION control 0: STPC control 1: Off 0: On 1: IR output carrier with duty cycle 75% 0: IR output without carrier MODE1.5 is for LED flash type control. MODE1.4 is for LED1 section control ON/OFF. MODE1.3 is for LED2 Section/STPC control. MODE1.2 is for LED1 volume control. MODE1.0 is for IR output with or without carrier and this bit is useful only MODE0.5 is "1". For STPC control IR output (MODE0.5 is 0), the IR output always has 38 KHz carrier signal no matter what the setting of MODE1.0 is. 3. PAGE Register BIT PAGE 7 6 5 4 PG4 3 PG3 2 PG2 1 PG1 0 PG0 DEFINITION
Bits 5-7 of PAGE register are reserved; bits 0-4 are used for page selection. The user must setup the page mode configuration described in the Option Control Function section. Once the page mode is decided, the working page is selected by the bits 0-4 of PAGE register. Hence, the user can execute "LD PAGE, value" instruction to change the working page of the voice entry group. Not all of the bits 0-4 of PAGE register are used in different page mode; they are listed below. PAGE MODE 1-page 8-page 16-page 32-page PG4 x x x PG3 x x PG2 x PG1 x PG0 x
Where "x" means dont care and "" means must be set properly.
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Preliminary W583XXX
4. EN0, EN1 Registers BIT EN0 EN1 7 TG4R TG8R 6 TG3R TG7R 5 TG2R TG6R 4 TG1R TG5R 3 TG4F TG8F 2 TG3F TG7F 1 TG2F TG6F 0 TG1F TG5F
A "1" means "enabled", while a "0" means "disabled" for that edge of the particular TG pin. For example, the instruction "LD EN0, 0x0F" enables all the falling edge triggers of TG1-TG4, while disabling all the rising edge triggers of TG1-TG4. The user can modify the EN0 and EN1 registers during operation of the W583xxx to achieve various kinds of trigger functions, like retriggerable or not, one shot or level hold play mode, etc. That is to say, users can change the contents of EN0, EN1 register during synthesis at will to determine which trigger pin is to be enabled or disabled for its falling/rising edge. EN1 register is not provided in W583S10. 5. STOP Register BIT STOP 7 STH 6 STG 5 STF 4 STE 3 STD 2 STC 1 STB 0 STA
The STOP register is used to control the status of the STPA-STPH pins. For example STB bit, the corresponding bit 1 of the STOP register is used to drive the output buffer of STPB pin, an inverted stage, to show its logic status. Notes that bits 5-7 of STOP register are reserved in W583S10. 6. R0-R7 Registers These eight registers function as general purpose registers. They can be used to hold interrupt vector/label. R0 is a special register which can be incremented by "INC" instruction.
Option Control Function
There are four types of option control in W583xxx. They can be determined by a declaration in the users program file, but can not be controlled by register.
FUNCTION MASK OPTION DECLARATION DEFPAGE 1 Page Mode Configuration Operation Mode Oscillator Frequency Voice Output Type DEFPAGE 8 DEFPAGE 16 DEFPAGE 32 NORMAL CPU OSC_3MHz OSC_1.5MHz VOUT_DAC VOUT_PWM DEFINITION 256 interrupt vector/label for 1 page, 1 page in total (1-page mode) 256 interrupt vector/label for 1 page, 8 pages in total (8-page mode) 128 interrupt vector/label for 1 page, 16 pages in total (16-page mode) 64 interrupt vector/label for 1 page, 32 pages in total (32-page mode) Normal mode operation CPU mode operation 3 MHz oscillator 1.5 MHz oscillator DAC (AUD) output PWM output
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Publication Release Date: March 1999 Revision A1
Preliminary W583XXX
"DEFPAGE" decides the page operation mode of W583xxx. The default setting of the page mode is 1-page mode. The 8-page, 16-page or 32-page mode must be declared in order to reach the interrupt vector/label from 256 to 2047 when the interrupt vector/label is beyond 0-255. The W583xxx can communicate with an external microprocessor through the simple serial CPU interface, which is the same as the W581xx series. The CPU interface consists of the TG1, TG2, and STPA/BUSY pins. "NORMAL" and "CPU" decide whether the operation mode of W583xxx will be normal mode or CPU mode. "OSC_3MHz" and "OSC_1.5MHz" select the frequency of the system clock. "VOUT_DAC" and "VOUT_PWM" select the voice output type.
Interrupt Vector Allocation
The W583xxx provides a total of 8 trigger inputs to communicate with the outside world. Each trigger pin can invoke 2 dedicate interrupt vectors depending on TG pin status. The table below show the relationship between TG pin status and interrupt vectors. Interrupt vectors 8-15 are not allocated for TG pins in W583S10 because only TG1-TG4 pins are provided in this chip. INTERRUPT VECTOR 0 1 2 3 4 5 6 7 32 TRIGGER SOURCE TG1F TG2F TG3F TG4F TG1R TG2R TG3R TG4R POI INTERRUPT VECTOR 8 9 10 11 12 13 14 15 TRIGGER SOURCE TG5F TG6F TG7F TG8F TG5R TG6R TG7R TG8R -
Instruction Set
There are two types of instruction in the W583xxx, unconditional and conditional instructions. The first type of instructions are executed immediately after they are issued. The second type of instructions are executed only when the conditions specified in the instruction are satisfied. All the instructions are listed in the following table. The cycle time for each instruction is 2/Sampling Frequency(Fs). For Fs = 6.0 KHz, the cycle time is 333 S. UNCONDITIONAL JP JP * LD LD G Rn EN0, value EN1, value * JP JP LD LD CONDITIONAL G Rn EN0, value EN1, value @STS @STS @STS @STS
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Preliminary W583XXX
Continued
LD LD LD LD END MV INC TX
MODEi, value STOP, value PAGE, value Rn, value Rn, Rm Rn
LD LD LD LD END MV INC TX
MODEi, value STOP, value PAGE, value Rn, value Rn, Rm Rn
@STS @STS @STS @STS @STS @STS @STS @STS
Legend: G: Interrupt vector/label Rn: R0-R7 Rm: R0-R7 MODEi: MODE0, MODE1 value: 8-bit data @STS can be the following: @LAST, @TGn_HIGH, @TGn_LOW, n = 1-8. But n = 1-4 for W583S10. *: These instructions are not provided in W583S10.
ABSOLUTE MAXIMUM RATINGS
PARAMETER Power Supply Input Voltage Storage Temp. Operating Temp. SYMBOL VDD-VSS VIN TSTG TOPR CONDITIONS All Inputs RATED VALUE -0.3 to +7.0 VSS -0.3 to VDD +0.3 -55 to +150 0 to +70 UNIT V V C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
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Publication Release Date: March 1999 Revision A1
Preliminary W583XXX
ELECTRICAL CHARACTERISTICS
(TA = 25 C, VSS = 0V, VDD = 4.5V unless otherwise specified.)
DC Characteristics
PARAMETER Operating Voltage Input Voltage SYM. VDD VIL VIH Standby Current ISB1 ISB2 Operating Current (Ring type) Operating Current (Crystal type) Input Current of TG1-TG8 Pins Input Current of TEST Pin Input Current of SEL, RESET SPK (D/A Full Scale) Output Current of STPA-STPH Output Current of SPK+, SPKIDAC IOL1 IOH1 IOL2 IOH2 VDD = 4.5V, Rl = 100 VDD = 3V, Vout = 0.4V VDD = 3V, Vout = 2.7V VDD = 3V, Rl = 8 -4.0 0.8 -0.8 100 -100 -5.0 -6.0 mA mA mA mA mA IIN3 VDD = 3V, Vin = 0V -8 A IIN2 VDD = 3V, Vin = 3V 50 A IOP1 IOP2 IOP3 IOP4 IIN1 VDD = 3V, All I/O pins unconnected, No Playing VDD = 5V, All I/O pins unconnected, No Playing VDD = 3V, No Load VDD = 5V, No Load VDD = 3V, No Load VDD = 5V, No Load VDD = 3V, Vin = 0V CONDITIONS MIN. 2.4 VSS -0.3 0.7 x VDD TYP. 3 MAX. 5.5 0.3 x VDD VDD 1 1 500 1 600 1.2 -8 A A A mA A mA A UNIT V V
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Preliminary W583XXX
AC Characteristics
PARAMETER Oscillation Frequency
1
SYM. Fosc Fosc Fosc Tins TPD TDEBL
2
CONDITIONS Ring Oscillator, Rosc = 750 K Ring Oscillator, Rosc = 1.6 M
MIN. 2.7 1.3
TYP. 3 1.5
MAX. 3.3 1.7 7.5
UNIT MHz
Oscillation Frequency Deviation by Voltage Drop Instruction Cycle Time POI Delay Time Long Debounce Time Short Debounce Time
2. For ring oscillator only.
F(3V)-F(2.4V) F(3V) Fosc = 3 MHz, SR = 6 KHz Fosc = 3 MHz Fosc = 3 MHz, SR = 6 KHz 50 400 1/3 160
%
mS mS mS S
TDEBS
1. This parameter is different from that of W58300.
TYPICAL APPLICATION CIRCUIT
VCC STPA/BUSY STPB LED2/STPC STPD STPE STPF STPG STPH VDD VDD1
IROUT TG1 W583S80 TG2 TG3/IRIN TG4 LED1 TG5 TG6 TG7 AUD/SPK+ TG8 SPK-
VCC
VCC
Rosc
OSC/XIN TEST XOUT RESET SEL VSS1 VSS
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Publication Release Date: March 1999 Revision A1
Preliminary W583XXX
BONDING PAD DIAGRAM
(For W583S10 only)
(0,0)
21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PAD NO. 1 2 3 4 5 6 7 8 9 10 11
PAD NAME VDD OSC OSCO TEST
RESET
PAD NO. 12 13 14 15 16 17 18 19 20 21 -
PAD NAME LED1 STPA/BUSY STPB LED2/STPC STPD STPE VSS1 VDD1 SPKAUD/SPK+ -
TG1 TG2 TG3/IRIN TG4 VSS IROUT
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Preliminary W583XXX
(For W583S15 to W583M02)
(0,0)
1 2 3 4 5 28 29
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
27
PAD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PAD NAME VDD OSC/XIN XOUT SEL TEST
RESET
PAD NO. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 -
PAD NAME IROUT LED1 STPA/BUSY STPB LED2/STPC STPD STPE STPF STPG STPH VSS1 VDD1 SPKAUD/SPK+ -
TG1 TG2 TG3/IRIN TG4 TG5 TG6 TG7 TG8 VSS
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Publication Release Date: March 1999 Revision A1
Preliminary W583XXX
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792697 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
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